The present invention relates to a flash memory device, and more specifically to a method of fabricating a flash memory device, in which the junction breakdown voltage (JBV) and the on-current margin of a high-voltage PMOS transistor can be improved.
In a NAND flash memory device, a high-voltage bias is used upon program/erase. In order to supply the high-voltage bias to a cell, a high-voltage transistor must be located at the end of the wordline and the bitline, so that a high-voltage can be smoothly applied.
In a single-level cell (hereinafter referred to as “SLC”) in which 1 bit is stored per cell, programming is performed in steps of 500 mV, from 16V to 19.5V. In a multi-level cell (hereinafter, referred to as “MLC”) in which two or more bits are stored per cell, however, cell distribution must be smaller than that of the SLC. Accordingly, a problem is presented by the narrowness of the process margin.
In order to solve this problem, a high-voltage PMOS transistor is used in the MLC in order to improve the cell threshold voltage distribution.
FIGS. 1a-1d are sectional views for illustrating a method of fabricating a flash memory device in the related art. The same reference numerals will be used to identify like or similar parts having the same function.
In order to fabricate the conventional flash memory device, an N-well is formed in a high-voltage PMOS transistor region of a P-type conductive semiconductor substrate. The semiconductor has two regions, a high-voltage PMOS transistor region and a low-voltage element region (or cell region). The semiconductor substrate 10 is divided into an active region and a field region by an isolation process.
Referring next to FIG. 1a, a tunnel oxide film 11a, a polysilicon film 11b for a floating gate, an interlayer dielectric film 11c, and a polysilicon film 11d for a control gate are laminated on the semiconductor substrate 10. The polysilicon film 11d for a control gate, the interlayer dielectric film 11c, and the polysilicon film 11b for a floating gate are selectively etched by photolithography, so that gates 11 are formed on the high-voltage PMOS transistor region and the low-voltage element region.
Thereafter, in order to mitigate damage to the gates 11 caused by the etch process, a re-oxide film 12 is formed on the lateral sides and the top surface of the gates 11 by a re-oxidation process.
As shown in FIG. 1b, a first photoresist layer PR1 is coated on the entire surface and is patterned by an exposure and development process, so that the high-voltage PMOS transistor region is exposed.
P− ions are then implanted using the patterned first photoresist layer PR1 as a mask, thus forming low-concentration P-type ion implant regions 13 in the N-well on both sides of the gate 11 of the high-voltage PMOS transistor region.
The low-concentration P-type ion implant region 13 functions to mitigate a JBV reduction phenomenon, which is generated due to a difference in the concentration between the N-well and a high-concentration P-type ion implant region to be formed later. At this time, the region 13 is formed at a low-concentration doping level.
Thereafter, as shown in FIG. 1c, P+ ions are implanted using the first photoresist layer PR1 as a mask, thus forming high-concentration P-type ion implant regions 14 in the low-concentration P-type ion implant region 13.
A source and drain junction of a Double Doped Drain (DDD) structure having the high-concentration P-type ion implant regions 14 surrounded by the low-concentration P-type ion implant regions 13 is completed thereby.
After the first photoresist layer PR1 is removed, a deep UV photoresist is coated on the entire surface as a second photoresist layer PR2. The second photoresist layer PR2 is then patterned to expose the low-voltage element region, as shown in FIG. 1d. 
An N-type ions, such as P31 and As75 ions, having a concentration of 1E13 ions/cm3 or less, is then implanted using the patterned second photoresist layer PR2 as a mask, thus forming low-concentration N-type ion implant regions 15 in the semiconductor substrate 10 on both sides of the gate 11 of the low-voltage element region.
Thereafter, though not shown in the drawing, the second photoresist layer PR2 is removed and a spacer is formed on both sides of the gate 11 of the high-voltage PMOS transistor region and the low-voltage element region. N+ ions are implanted into the semiconductor substrate 10 on both sides of the gate 11 and the spacer of the low-voltage element region, thus forming a high-concentration N-type ion implant region.
In order for a high-concentration PMOS transistor to maintain a high junction breakdown (JBV), the concentration of the low-concentration P-type ion implant region 13 needs to be low. However, if the concentration of the P-type ion implant region 13 is low, there are less charge carriers available for current and results in reducing the on-current of the high-voltage PMOS transistor.